TRNENSEL=0, BRDYM=0, EDGESTS=0
SOF Output Configuration Register
| EDGESTS | Edge Interrupt Output Status Monitor 0 (0): before stopping the clock supply to the USB module 1 (1): the edge interrupt output signal is in the middle of the edge processing |
| BRDYM | BRDY Interrupt Status Clear Timing 0 (0): Software clears the status. 1 (1): The USB clears the status when data has been read from the FIFO buffer or data has been written to the FIFO buffer. |
| TRNENSEL | Transaction-Enabled Time Select 0 (0): For non-low-speed communication 1 (1): For low-speed communication |